» "Engineers gather no moss and new approaches and techniques can sometimes change everything. We may have that case here with the eASIC announcement," says eeProductCenter's Jon Gabay. But MathStar's offering of a s new 1 GHz Field Programmable Object Array (FPOA) were a close second, according to our readers. Jon calls MathStar's product "pretty impressive."

(1)
EASIC
Is it an ASIC, an FPGA, or an ASIC with and FPGA?
eeProductCenter's Stephan Ohr says: "eASIC has an interesting approach. The architecture is an array of embedded configurable logic blocks called eASICores. The logic cells (eCells) use SRAM based LUTs (Look Up Tables) and flip-flops which allow dynamic or power up configuration, just like many of today's RAM based, LUT based FPGAs. What brings this to a new level is that the eCells are inter-connected by a wiring grid exclusively done on the upper metal layers. This allows a design to be customized by only generating one mask layer which merely consists of vias that do the interconnection. As a result, while they do not provide instant turn around like a desktop FPGA development system, turn around is very fast compared to a full fledged ASIC. What's more, the company states there is no NRE associated with the design and production using this approach. The single Via-customization means that an alternative lithography approach like Direct-write eBeam can be used to eliminate the customization tooling cost, shorten time-to-market and add manufacturing flexibility. What's a bit more subtle here is what this allows us to do. Instead of using and FPGA and IP processor or peripheral cores, we can now design our own hardwired functionality and put in configurable or reconfigurable logic as we see fit. "
Readers say: » "It would be interesting to compare eASIC's solution with other structured ASICs on the market" » "eASIC is the only company doing this according to the article. It's not good that you must buy only their chips and IP." » "Looks like it provides an intermediate cost option between large FPGAs and pure ASICs. But with routing determined by mask, I would think that volatile LUT configuration would be of limited utility. (Don't know many tools that give you the flexibility to work with LUT changes once routing is fixed.) So it would seem system cost would be improved if they could integrate (via a ROM programmed by the same mask as the routing, or via flash) non-volatile, live-at-power-up LUT configuration." » "I think that this a step in the right direction. If die size can be minimized, that should keep pricing to an acceptable level." » "Great technology, saves development time and time to market, hope will go down in price." » "Going from FPGA to ASIC, we expect a performance increase, about a 40%-plus power decrease and a big cost cut. It does not seem like this device would give us all that, just by its architecture. Modern day designs emphasize run-time reconfigurability which I do not see in this device. " » "Looks like a neat technology. I am familiar with LSI's RapidChip and see these two technologies competing." » "Seems like it would require a very 'niche' market."
USABILITY RANK: 1

(2)
MATHSTAR
What a difference a Gig Makes
eeProductCenter's Stephan Ohr says: "Designing high speed logic is an art unto itself. Anyone who has pushed the envelope, even just a bit, knows the trials and tribulations of transmission line characterization, termination, and even matching trace lengths precisely to minimize skew. I've worked on boards where a 1/2 inch of extra trace length was enough to throw synchronization off and make all the difference. While tools have definitely gotten much better at performing parametric extraction and high speed static timing analysis, there is still much to learn by trial and error and experience, unless, you can fit all your high speed crunching in a single chip. That's what MathStar is offering with it's new 1 GHz Field Programmable Object Arrays (FPOAs). These are pretty impressive. FPOA's are a medium-grained heterogeneous array composed of hundreds of individual processing elements. Each element is called a Silicon Object which has its own program and data memories and operates without the aid of global intervention. Inside the array, the data paths and control paths are for the most part separate but still coupled. The data path is 16 bits wide while the control path is bit-wise granular, but multiple objects can be combined to create wider data paths. "
Readers say: » "Quality of development tools and the device cost will make or break the silicon scheme." » "What is the I/O architecture? How are the eight instructions controlled? How is data directed between 'Silicon Objects'? What style of programming is required? All I know is that there are a lot of processing blocks, which somehow take unspecified instructions, which communicate with each other somehow..." » "Still need to evaluate it. There's not a comparision in term of cost/sizes to current FPGA products." » "Cool." » "Looks very interesting. I like parts like this that provide higher-than-gate-level abstraction." » "Really need to see cost and availability numbers. There is no way to judge how real this is or if the design software is adequate." » "If Moore's lay stays intact these could start to make a difference in 4/5 years. I would like to see 10,000 elements for these to start to have an impact. However, the article did not specify how much each processing element could handle, how much memory is integrated into each element and internally. and how much external memory is in there. My 10K element requirement is probably way off without this information." » "Math routines are necessary, with implementation dependent on the architecture at hand, but generalized routines are almost as good as optimum. ..certainly less costly.." » "It sounds like getting the best of both worlds! I'll have to look into it further. Can't tell how usable and stable the product is." » "This is something that I had in mind for many years -- an array of reprogrammable processing units on chip that can be linked for different applications. However, eight instructions per silicon object is too limited. I expect these objects to be higher integrated ones (like an array of DSPs or small processors.) To me, the current FPOA is geared for math computation, not really for general purpose applications." » "An impressive combination of innovations." » "This is the future, with changes made by software upgrades. Great idea" » "This is potentially very big."
USABILITY RANK: 3

(3)
SMC
God Bless USB: SMSC's port hub may open millions of new slots
eeProductCenter's Stephan Ohr says: "The USB2502 Controller is a two-port integrated device designed to replace (or lower the cost of) a 4-port implementation. Why pay for a four ports, when your USB hub may only need two? The two-port USB2.0 Hub device supports USB high-speed (HS, 480-Mbits/s), full-speed (FS, 12 Mbits/s) and low-speed (LS, 1.5 Mbits/s) data rates For USB bus-powered operation, an on-chip voltage 1.8V regulator powers the core of the controller. The I/O is 3.3 volts, but will tolerate a full 5 volts. In portable computers, the controller can be configured via an SMBus, or with EEPROM (even pin-strapping). "
Readers say: » "This could make it cost effective to add connectivity to a wide range of devices." » "Nice product. I believe it will help drive acceptance and usage of 2.0 peripherals." » "Would be MUCH more likely to use the USB20H04 4-port hub controller instead." » "As a PC user, I'd rather have a hub with extra (unused) ports than two smaller hubs and extra wiring. Building the two-port hub into a product (printer, etc.) for daisychaining makes some sense, however. But I've also seen bad experiences with USB-interfaced products from Microsoft that would only work when connected directly, and failed when going through a hub. This (and hub depth with daisy chaining) makes me less excited about using more smaller hubs instead of fewer larger hubs." » "Very good product for nice price" » "About time. Daisy chaining of peripherals is long overdue." » "I like to keep everything simple, so I would like to have only one type of connector for everything, So hopefully manufacturers will keep that in mind that way we do not need to buy so many controllers and adapters to connect and control every device we have" » "Really great that the device can be powered off, yet still interface to a device down the chain. Must be a great cost benefit, or it will not be worth it. Thanks." » "Sounds cool, but it's more of a consumer product than a business device" » "Good technology that's likely going to run into wireless competition." » "Looks like a well-priced and well-thought out solution."
USABILITY RANK: 2

(4)
ALTERA
Customizing a Standard
eeProductCenter's Stephan Ohr says: "The Nios II is a family of 32-bit RISC based soft processor cores. The 200 DMIPS performance range is being offered in three flavors. One is optimized for maximum performance and takes a bit more space and power. One is optimized for minimum logic usage, and the last one falls somewhere in between. The NIOS processors are made to map into the Cyclone, Stratix and HardCopy structured ASIC families. All cores are code compatible allowing designers to swap as requirements or directions change without too much impact on code development. I like the rich assortment of peripheral functions that are available to bolt onto the NIOS family. "
Readers say: » "It's intriguing but hard to imagine switching.Too many of the peripherals are needed from 3rd parties." » "Nice to have this core in FPGA " » "There is always concern about tool/support of embedded microprocessors. Also, after the prototype, if the design is ported to ASIC, howęs performance and power consumption of this special cpu compared up to that of ARM?"
USABILITY RANK: 5

(5)
ANALOG DEVICES
Bi-directional eight-channel level translator guarantees up to 40-Mbps data transfer
eeProductCenter's Paul O'Shea says: "A new series of digital switches allowa a single IC to provide bi-directional data transfer and voltage translation. Its 8 channels, by allowing a mix of simultaneous read and write functions with bi-directional data transfer, provide designers greater flexibility and efficiency over traditional bus switches that require separate read/write cycles. The ADG3308's advanced circuit integration also reduces design work and saves board space, making it an ideal solution for portable consumer applications such as cell phones and notebook computers. The ADG3308 guarantees direct data transfer between devices operating from supplies as different as 1.2-V and 5.5-V. This large voltage translation range allows analog or digital devices having widely differing logic levels to communicate seamlessly in the smallest possible board area without losing data. "
Readers say: » "Looks like a very useful part" » "Looks like a good solution. What is the max time required to switch data directionS?" » "Price seems high; standard logic from FSC and TI is much less costly" » "Some interesting possibilities."
USABILITY RANK: 4

(6)
FUJITSU
It's a Hat, a Broach, a Pterodactyl, An FPGA, A Processors....
eeProductCenter's Stephan Ohr says: "IPFlex and Fujitsu have jointly announced the DAP/DNAR-2 (Digital Application Processor/Distributed Network Architecture), a unique part that has the ability to dynamically reconfigure its internal circuitry. It is touted as being able to perform multiple processing tasks within a single-chip that previously required several specialized chips. The 'instantly reconfigurable' internal circuitry of the DAP/DNA-2 combines a microprocessor that contains multiple processing elements (PEs). The ability to optimally configure internal circuits lets designers tailor the internal architecture to best suit a specific application. The function of each PE, as well as connections among PEs, can be reconfigured not only when building the system, but also when it is running, enabling instant (within one clock cycle) reconfiguration to suit the application at hand. The DAP/DNA-2 lays out these PEs in a two-dimensional array so that it can quickly and flexibly change their function and the connections between them. "
Readers say: » "There are FPGAs with built-in processor cores and reconfigurabilities on market already. Unless this device is extremely easy to use, flexible, low power and cheap, I do not think it would stand out." » "The technical significance could be relatively high if it is a real device. Mental flashbacks to self modifying code give me pause." » "The ability to reconfigure instantly and on-the-fly is a nice feature."
USABILITY RANK: 8

(7)
LATTICE SEMICONDUCTOR
Programmable clock generator offers flexible skew control
eeProductCenter's Paul O'Shea says: "The first devices in the ispClock5500 family, the 10-output ispClock5510 and 20-output ispClock5520, combine a high- performance clock generator with a flexible, Universal Fan-out Buffer. The on-chip clock generator can provide up to 5 clock frequencies ranging from 10MHz to 320MHz using a high-performance PLL and clock multiply and divide facilities. The Universal Fan-out Buffer can drive up to 20 clock nets using either single-ended or differential signaling, with individual output control for improved signal and timing integrity. "
Readers say: » "Excellent part, but I do have some questions concerning the clock outputs jitter spec." » "Currently we use a couple of oscillators at the same time. By using this product, we will simplify the design and save spaces on the PCB" » "Very nice device, the jitter and skew numbers are decent."
USABILITY RANK: 6

(8)
TEXAS INSTRUMENTS
Wide bandwidth video switches optimize RGB and composite video
eeProductCenter's Stephan Ohr says: "These new additions to the TS family of signal switches, the TS5V330 and the TS3V330, are Quad Single-Pole Double-Throw (SPDT) video switches. The TS5V330 supports an operating range from 4.5V to 5.5V, while the TS3V330 is a lower-voltage component, operational from 3.0V to 3.6V. Leveraging its extensive expertise and knowledge in digital switch design and advanced process technology, TI is targeting the devices at high frequency video applications, such as multiplexing/demultiplexing video signals on VGA cards. Both devices are also fully specified for partial-power-down applications (using Ioff.) Specified for composite and RGB video applications, the TS5V330 and the TS3V330 offer low differential gain and phase shift. "
Readers say: » "Technical specification are limited, more data would be useful." » "With the wide bandwidth and low R(on), these might be useful for non-video apps as well."
USABILITY RANK: 7

(9)
PERICOM
Pericom hopes to carve memory and backplane slots with 500MHz bus switches
eeProductCenter's Stephan Ohr says: "Called "NanoSwitch that," these devices are targeted toward new-generation servers, RAID storage cabinets, super VGA graphics card, and memory bank switching, as well as high-performance networking/telecom backplanes. The company says its PI3CH family of high-bandwidth (500MHz) bus switches will also serve communication buses like PCI-X, and emerging DDR-I / DDR-2 memory standards. Such switching may also enable I/O migration from parallel to serial differential signaling standards. Key performance features in this product family include very flat On-Resistance (5 Ohms) across the full device bandwidth, and very low On/Off Capacitance (5-10pF) that enables the Switches to be used in applications to reduce bus loading. "
Readers say:
USABILITY RANK: 9

(10)
TEXAS INSTRUMENTS
2 Gb/s crosspoint switches ideal for clock buffering, data transmission
eeProductCenter's Paul O'Shea says: "These two new 4x4 non-blocking crosspoint switches operate at more than 2.0 gigabits per second (Gbps). The devices come in a flow-through pin-out, which allows for ease in printed circuit board (PCB) layout. Low-voltage differential signaling (LVDS) outputs are used to achieve a high-speed data throughput while using low power. The devices are ideal for clock buffering and muxing or data transmission in datacom and telecom applications such as high-speed network routing and wireless base stations. Each output driver of the SN65LVDS250 and SN65LVDT250 includes a 4:1 multiplexer to allow any input to be routed to any output. "
Readers say:
USABILITY RANK: 10