Synplify Premier

TechOnline (11/02/2006 6:01 PM ET)

Synplicity's Synplify Premier software is the ultimate FPGA design and debug solution. It builds upon Synplicity's industry leading synthesis technology and adds new graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. Synplicity invented graph-based physical synthesis to improve timing closure by means of a single-pass physical synthesis flow for 90nm FPGAs. In FPGAs, unlike ASICs, proximity does not imply better timing. The essence of the graph-based approach is that preexisting wires, switches and placement sites used for routing an FPGA can be represented as a detailed routing resource graph. The notion of distance then changes to a measure of delay and availability of wires. The Synplify Premier tool's graph-based physical synthesis technology merges optimization, placement and routing to generate a fully placed and physically optimized netlist, providing rapid timing closure and a 5% to 20% timing improvement. In addition, the Synplify Premier product offers the most efficient method of in-system verification of FPGAs. Instrumented signal values from a live, running FPGA are annotated directly into the Verilog or VHDL source. The Synplify Premier software dramatically accelerates the debug process and provides a rapid and incremental method for finding elusive design problems.

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