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The LogiCORE RapidIO Logical Layer interface is pre-implemented and fully tested module for Xilinx Virtex-II and Virtex-II Pro series FPGAs. Critical paths are controlled by a constraints file that ensures predictable timing and significantly reduces the engineering time required to implement the Logical (I/O) and Transport Layer portion of a design. Resources can instead be focused on unique user application logical in the FPGA and on the system level design. As a result, the Xilinx RapidIO Logical (I/O) and Transport products can minimize your product development time.
For more information about the LogiCORE RapidIO Logical Layer Interface, visit
Xilinx's Web site
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