ARM9-based MCU line touts upgrade path from ARM7 devices

Marty Gold

eeProductCenter (05/26/2006 10:18 AM ET)

San Jose, Calif. — Targeting system designers that have outgrown the ARM7 type processors, Atmel Corp. has launched its SAM9 family of 32-bit microcontrollers based on the ARM926EJ-S core. The AT91SAM9260 is the first member of the new family that shares the same integration levels and programming models as Atmel’s ARM7-based MCUs, allowing direct migration between controllers based on different ARM cores.

The pin-compatible SAM9 MCUs have all the features required for real-time embedded control applications, including an on-chip RC-oscillator, real-time clock, watchdog timer, power-on-reset, brown-out-detect, an 8-level 32-source priority interrupt controller, DMA, and single cycle instruction fetch.

These MCUs are said to be the first ARM9-based microcontrollers with flash memory integrated on the same chip. They are said to be the only flash-based ARM9 microcontrollers on the market with small footprint RTOS support. A variety of family members will be announced in 2006 and 2007 with flash memory densities ranging up to 1024 Kbytes. Integrated Flash memory offers better performance and lower power consumption versus stacked die implementations.

As embedded systems evolve, new software-based features are added, such as encryption, file systems, GPS, audio, or wired and wireless networking, increasing the processing load on the MCU. In addition, the amount of data that must be processed also tends to increase as more communications links are integrated in a single chip. Finally, designers frequently migrate to more advanced algorithms that require more computation. The basic application doesn’t change: it is just better, more accurate, more fully featured, and requires much more bandwidth to execute.

One example of this is a point-of-sale terminal, which requires around 10 seconds to secure a communication link with a trusted party using a 20 MIPS ARM7 microcontroller running 1024-bit RSA encryption in software. An implementation based on an ARM9 microcontroller completes the negotiation in less than a second and leaves plenty of processing power to manage high speed wired or wireless network stacks. Customers really feel the difference when cash register lines go faster, ultimately the retailer might see increase in sales.

Until now, getting the extra throughput has meant re-doing the design from scratch using a high-throughput ASSP, with no support for real-time execution and that requires the use of an complex and difficult to learn operating system, such as Linux or WinCE. The lack of system integration in ASSPs forces significant hardware redesign including addition of multiple external components, with adverse effects on system cost and board level estate.

The majority of ARM9-based processors are designed for large memory footprint operating system (OS) such as Linux or Win CE. These OSs are overkill in the vast majority of embedded control applications, and they are difficult to learn and use. They fully rely on non-deterministic cache memories to hit the performance targets and handle interrupt priorities in software. This is incompatible with the Real-Time embedded system constraints of many customers.

Although the prevalence of C/C++ for programming radically improves the portability of software from one processor to another, ARM processors with compatible instruction sets have different peripheral sets, making migration quite difficult and time consuming. The hardware abstraction layer must be re-written from scratch and a different operating system to be used, creating unacceptable extra work.

Atmel’s ARM7- and ARM9-based controllers both have peripheral DMA controllers (PDCs) that off-loads data transfers between peripherals and memories, from the CPU. Such transfers can quickly overload any processor. For example, at 4 Mbps, a 50 MHz ARM7 is using all its MIPS for data transfer. At 200 MHz, ARM9 runs out of gas at just 16 Mbps. When you consider that there are seven UARTS, a USB and Ethernet interface in a point-of-sale system, and each of them has a data rate of up to 100 Mbps, it’s clear that a lot of applications will outgrow even a conventional 200 MHz ARM9 without DMA support.

Atmel is the only vendor of ARM-based controllers to support migration between MCUs based on different ARM cores and to provide the option of deterministic, real time operation. Designers are completely relieved of the cumbersome task of re-writing the hardware abstraction layer, peripheral drivers and real time operating systems, as is, typically required when moving to another controller family. The SAM9260 also offers supervisory functions and has third-party RTOS support comparable to those of 8/16-bit controllers.

Developed for highly connected image processing applications, such as point of sale terminals, Ethernet based IP cameras, and 2-D bar code readers, the SAM9260 integrates a 200 MIPS ARM926EJ-S core with a camera interface, seven USARTS, 10/100 Ethernet MAC, 12 Mbps USB device and host controller with on-chip transceivers, external bus interface supporting SDRAM, Flash, NAND Flash with built-in ECC, SDIO, and multimedia card interface (MMC), three synchronous serial controllers (SSC), two master/slave Serial Peripheral Interfaces (SPI), a three-channel 16-bit timer/counter, two-wire interface (TWI) and IEEE 1149.1 JTAG boundary scan on all digital pins.

Embedded systems, such as POS or bar code readers are connected to myriad external devices. For example, a typical POS system includes synchronous/asynchronous serial interfaces to its LCD panel, smart cards, wireless transmission devices (802.11, Bluetooth, GSM, DECT) and/or infrared devices. At about 75c each in volume quantities, the six or seven USARTs required for these systems would cost about $5. The AT91SAM9260 integrates seven USARTS on this near-$6 controller. Four USARTs have individual baud rate generators, IrDA infrared modulation/demodulation, Manchester encoding/decoding, ISO7816 T0/T1 smart card addressing support, hardware handshaking and RS485 control. Full modem control signals are provided on USART0. In addition there are two Txd/Rxd UARTs and a debug UART which can be used as a normal UART too.

The image sensor interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8 and RGB 5:6:5. Synchronization to external sensors is accomplished by horizontal and vertical sync signals or the standard SAV, EAV embedded synchronization data. YCrCb to RGB color space conversion is done automatically in Hardware. The conversion matrix is fully programmable. Built in FIFOs and DMA minimize processor intervention and reduce system power consumption. Image Sensors can be clocked by an external source or by the AT91SAM9260. If clocked by the SAM9260 the pixel clock to the sensor can be managed under software controller further reducing system power consumption when the sensor is not in use.

The AT91SAM9260 10/100 Base-T Ethernet MAC resides as a master on the multilayer AHB matrix. Separate 28-byte transmit and receive FIFO’s along with separate DMA channels for transmit and receive facilitate data management from the MAC to internal or external memory. Interfacing to external PHYs is accomplished through the MII compliant or RMII compliant interface. The built in address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. The statistics register block contains registers for counting various types of event associated with transmit and receive operations. These registers, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with IEEE 802.3.

The USB device port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Integrated on-chip transceiver and 2432 byte FIFO maximize integration and data throughput. Six Configurable endpoints are available with Ping Pong mode support for isochronous transfer.

The USB host port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. The standard OHCI USB stack driver can be easily ported to Atmel’s architecture in the same way all existing class drivers run without hardware specialization.

A 10-bit, four-channel successive approximation analog-to-digital converter (ADC) converts 312,000 10-bit samples per second with -2/+2 LSB integral non linearity, -1/+2 LSB differential non-linearity and individual enable and disable of each channel. An external voltage reference provides better accuracy on low voltage inputs. Trigger sources include both hardware and software triggers built in automatic sleep-after-conversion and wakeup-on-trigger modes offer the system designer choices for managing their power budget.

Like SAM7 controllers, the AT91SAM9260 has a system controller with a full complement of supervisory functions that includes an 8-level priority interrupt controller, 32 KHz oscillator, PLLs, real-time periodic interval and watchdog timers, reset and shutdown controllers, and backup registers. The system controller help reduces power consumption by providing configurable clocks to the processor core and each of the on-chip peripherals at the lowest possible clock frequency. The shutdown controller puts the processor in an ultra low power mode, typically less than 10uA. Highly critical interrupt routines can be locked in the 16k Byte instruction cache guaranteeing a deterministic response time to interrupts.

The internal bus bandwidth of the AT91SAM9260 is maximized by 24 DMA channels and a five-layer high-speed bus matrix. It connects all masters and slaves in the system in a parallel fashion and enables data transfers between peripherals and on- and off-chip memories without any CPU intervention.

A programmable arbiter manages the priorities between the bus masters. Masters include the 926EJ-S address and data busses for code and data space, EMAC DMA, USB Host DMA, ISI DMA, and peripheral data controller DMA. Slaves include the 32 KByte SAMB-BA boot ROM, 2 separate 4k byte on chip SRAM’s, the Peripheral Bridge and the External Bus Interface. The 24 channels of the peripheral DMA are mapped in the memory of each peripheral, greatly simplifying the peripheral drivers.

For the details of the device, see block diagram below.

The AT91SAM9260 has third-party RTOS support from Green Hills Software, Mentor Graphics and Micrium. Compiler/debuggers are available from Green Hills Software, ARM, Keil, IAR Systems and any compliant ARM926EJ-S compiler. WINCE and Linux operating system support is also provided.

The AT91SAM9260 is available now in a 208-pin Green QFP and 217-ball LFBGA RoHS-compliant package and is priced near $6 in quantities of 100,000. Additional members of the SAM9 family will be available in late 2006 and 2007.

Atmel Corp. (408) 441-0311

www.atmel.com.