FPGA-based reference design enables video-over-IP

Ismini Scouras

eeProductCenter (04/11/2005 10:34 AM ET)

San Jose, Calif. — By leveraging the programmability of its Cyclone FPGA series and Nios II embedded processor, Altera Corp. has developed the first FPGA-based, video-over-Internet Protocol (IP) reference design to help engineers accelerate the development of cost-effective, low-complexity systems in the emerging video-over-IP market.

Video-over-IP is a digital technology for transporting video over IP-based networks. The new reference design, which can be used with any of Altera's FPGAs, targets applications for broadcast head-end and audio/video delivery systems.

By using Altera's latest product to build their broadcast systems, manufacturers can lower costs since they no longer need to design an ASSP into their systems.

The reference design can accept a configurable number of MPEG-2 transport streams and encapsulate the data for transmission over Ethernet. It can also regenerate a configurable number of transport streams using encapsulated data received from Ethernet.

A hardware engine is included to perform user datagram protocol (UDP) and option real-time transport protocol (RTP) encapsulation of the video data, which allows it to achieve a full Gigabit line rate. And the Nios II processor and driver software for BSD IP stack running under the eCos RTOS manage the network connection, initiate multicast sessions, and provide operational statistics.

Customers can make a request for the reference design code at the following Website: www.altera.com/videooveriprefdesign

Altera Corp., 1-408-544-7000, www.altera.com