(Reduced Instruction Set Computer) A computer architecture that reduces chip complexity by using simpler instructions. RISC compilers have to generate software routines to perform the equivalent processing performed by more comprehensive instructions in "complex instruction set computers" (CISC computers).
No Microcode
In a RISC computer, there is no microcode layer, and the associated overhead of that translation is eliminated. RISC keeps instruction size constant and bans the indirect addressing mode. It retains only those instructions that can be overlapped and made to execute in one machine cycle or less.
RISC designs date back to the 1960s; however, commercial RISC CPUs became popular with chips from companies such as MIPS and Sun in the late 1980s. When first introduced, RISC CPUs were typically faster than their CISC competitors; however, advancements in CISC chip technology over the years narrowed the performance differences, and marketing played a vital role. For example, the CISC-based x86 architecture, which debuted in the early 1980s, grew exponentially due to ever expanding personal computer usage. Even the RISC-based PowerPC chips used in Apple's computer line for more than a decade gave way to CISC-based x86 chips in 2006 (see Mactel).
RISC Vs. CISC
The RISC machine executes instructions faster because it does not have to go through a microcode conversion layer. The RISC compiler generates more instructions than the CISC compiler for the same processing. See microcode.
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