The design of LVDS interface for a Multi-Channel A/D Converter By John Z. WU, Sr. Application Engineer, Texas Instruments

John Z. WU, Sr. Application Engineer, Texas Instruments

ChipCenter (09/21/2003 3:00 PM ET)

This article analyzes system design specifications for a low-voltage differential serial output interface of a multi-channel, high-speed analog-to-digital (A/D) converter. Maximum data speed is presented as a function of slew rate, clock jitter, interface BER, skew and eye diagram margin. In addition, to increase the interface speed limitation, a non-standard low voltage differential signaling (LVDS) scenario is proposed.

For A/D application and design, the two most important specifications have always been bit resolution and data sample rate. However, the specification of an output data interface has become increasingly important, since a 3.3/5V CMOS single-end parallel interface is no longer the default output choice. The specification of an A/D output interface becomes even more important than power dissipation in some system applications, because of the emergence of more than 4 A/D converters on the same chip that needs an output serial interface with Double Data Rate higher than 500MBPS, and the serial interface can be designed with many possibilities such as a differential LVDS/LVPECL (Low-Voltage Positive Emitter Coupled Logic) or single-end LVCMOS, as well as an embedded or non-embedded clock architecture.

At very high speeds, for a single-ended CMOS 3.3V or 5V design, voltage swings of an A/D converter output generate electromagnetic interference (EMI), and suffer the impact of common mode noise. The EMI and common mode noise both limit the dynamic performance of a CMOS output interface.

The typical applications of LVDS can be found in telecom, such as a base station, access equipment, transmission equipment, Ethernet switches; and in the PC industry, such as a notebook, desktop, and workstation; and in medical equipment for ultrasound. The main factors driving the trend toward a high-speed low voltage differential serial interface are increasing the transmitted data speed limitation, decreasing the transmitted power consumption, and reducing EMI created by the transmission signals.

The LVDS is designed to achieve the above targets. LVDS technology uses a low voltage signal swing (250mV to 450mV) that limits power dissipation, while reducing radiation of EMI signals. The differential signaling provides many benefits over single-ended signaling, such as common mode rejection and magnetic canceling.

Chip-to-chip interconnection model and clock architecture
In order to design and develop an ultra high-speed data transmission serislizer and deserializer that are built into an AD converter, an ASIC and FPGA, the model of a chip-to-chip communication must be clearly described. The recommended model used in this article is the existing Open Systems Interconnection (OSI) reference model as defined by the International Standards Organization. The relation of LVDS transmitter and receiver with the ISO OSI reference model is shown in Figure 1.

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Figure 1. Chip-to-chip interconnection model

The first layer is the physical layer. It defines the physical and electrical characteristics of the interface model. The main design issues are to define reasonable voltage levels to represent logic bit 1 and bit 0, single-ended or differential signaling, as well as to specify bit time. The physical layer only accepts and transmits a stream of bits without any regard to the meaning or structure of the raw data.

The second layer is the data link layer. Its first task is to create and recognize frame boundaries. This task can be accomplished by attaching special bit patterns to the beginning and end of the frame. The second task is to combine the raw data into frames, and typically a few hundred or a few thousand bytes of raw data are combined into one data frame. Thirdly, this layer implements an error management, if a noise burst on the transmission line destroys some bits of a frame, then cyclic redundancy check (CRC) can detect those bits error, and the data link layer on the transmitter can re-transmit the frame.

Below the physical layer is the transmission media, such as the PCB trace for chip-to-chip interface on the PCB, and the coax cable or optical fiber that links a transmitter to a receiver which is located in a different chassis.

So far all designed high-speed interface between an AD converter and the subsequent stage (ASIC or FPGA) only involve the implementation of the first layer. Therefore, the following LVDS discussion will only focus on the physical layer. However, HyperTransport interface implements multi-layer functions and RocketIO interface provides the functions of the physical layer and the data link layer.

A source-synchronous communication interface is one in which a receiver needs to be synchronized by a transmitter clock. A data clock and frame clock can be sent out to a receiver from a transmitter in clock links, such as an example with one data clock and data n channel is shown in Figure 2. This clock architecture will be used in the following discussion.

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Figure 2. Multi-Channel A/D output serial interface function diagram

Another clock architecture is a transmitter clock that can be embedded into a data link; it is called embedded clock architecture. An embedded clock transmitter does not send a data clock or a frame clock to a receiver. Transmitter clock information is embedded into data frames by adding a start bit pattern and a stop bit pattern. Thus a receiver will recover the transmitted data and frame clock from the start and stop bit pattern.

In the case of a single channel and long data frame (more than 1k bits), embedded clock architecture has some advantages over non-embedded clock architecture by saving clock transmission links. But the special bit patterns added to the beginning and the end of a data frame will reduce the transmission speed, especially for a very short data frame. For example, when two overhead bits, one start bit and one stop bit, are added to every 12-bit long data frame the transmission speed will be reduced by around 14%.

Standard LVDS Interface
The standard for LVDS only specifies the electrical characteristics of the physical layer for low voltage differential signaling interface circuits. The requirements of the data link layer and the layers above are intentionally not specified in the LVDS standard and are left to manufactures to implement on demand.

A typical LVDS transmitter and a receiver are shown in Figures 3 and 4. The LVDS transmitter is a current source with a common-mode feedback. The passive RC pole-zero compensation network can be replaced by an on-chip capacitance. General current source output impedance is required very high with respect to variable load impedance. But LVDS interface load impedance has been specified as 100 ohms, one 100-ohm termination resistor must be add at the receiver side. If a long link is used for the interface, such as a PCB microstrip length of more than 2 inches, and with a data speed over 600MBPS, a transmitter termination is recommended so that less loop reflection and a good quality eye diagram can be achieved on the link.

Figure 3. LVDS Transmitter

Figure 4. LVDS Receiver

Under certain EMI restriction conditions, the maximum achievable data speed is limited by slew rate, clock jitter, and skew of the interconnected devices.

Because the clock jitter and skew can affect data sampling error and limit the maximum data speed of an LVDS interface, the following discussion will focus on the impact of clock jitter and multi-channel skew, the minimum data sampling timing window of a LVDS receiver, and the margins of a bit time and differential signal amplitude.

Receiver bit-valid timing window (Rx)
The minimum required bit-valid timing window at the input of a receiver device is expressed as follows equation 1: Rx = R_samp + R_clkjitter + R_clkskew + R_pkgskew

Here, the sampling time period R_samp includes a total time period of setup, hold time, the worst-case duty-cycle distortion, clock phase shift resolution, and the sampling error of receiver input registers across voltage, temperature, and process. The R_samp value can vary with a different de-skew scheme built-into an ASIC or FPGA. For Xilinx Virtex II PPGA, the typical value is 200ps. The R_clkjitter indicates DLL clock jitter in a receiver, and it dominates the receiver bit-valid timing window. The clock jitter is not correlated with a transmitter clock jitter. The minimum clock jitter peak-to-peak value is 200ps for a FPGA.

The R_clkskew represents the worst-case clock-tree skew observable between any two channels. For multi-channel, the R_ckskew of Xilinx Virtex II FPGA can vary from 25 to 500ps. But for single channel, this value can be eliminated.

The R_pkgskew represents the worst-case skew between any two balls of a package, shortest flight time to longest flight time from Pad to Ball (7.1ps per mm). This value is determined by the package size of a device. The package skew of a FPGA receiver may vary from 20 to 200ps with a multi-channel case.

Transmitter bit-valid timing window (Tx)
The maximum transmission bit-valid timing window (T_x) can be calculated as equation 2: T_x=Tb-[T_rise + T_fall + T_clkjitter + T_chskew + T_pkgskew + T_pcbskew]

Where: 1) The Tb represents bit time of a required maximum transmission data speed. 2) T_rise and T_fall represent a bit rise and fall time at input pin of a receiver, which include all parasitic capacitance impacts of a transmitter, receiver and link. 3) The T_clkjitter represents a peak-to-peak jitter of a transmitter output clock. 4) The T_chskew represents a transmitter channel-to-channel skew in bare die. 5) The T_pkgskew represents the worst-case skew between any two pins of a transmitter package. 6) T_pcbskew represents the skew of PCB trace length.

Eye diagram margin
The lower Bit Error Rate (BER) requires a bigger eye diagram margin. An eye diagram margin is determined in two dimensions, a valid timing margin and a valid amplitude margin of an interface. The eye diagram margin is a noise margin that a receiver can tolerate and still reliably receive data. This eye diagram margin includes various environment and systematic factors, such as power supply noise, EMI, cross talk, temperature, and process.

The timing margin (T_margin) of an interface is the difference between the maximum available transmitter bit-valid time and the minimum receiver bit-valid time as shown by equation 3: T_margin = T_x-R_x

At receiver input the difference between the maximum available voltage and the minimum threshold voltage is the amplitude margin as equation 4: A_margin = A_available − A_threshold

The eye diagram margin is shown in Figure 5, and it is a function of timing margin and amplitude margin as in equation 5: E_margin = F (T_margin, A_margin).

Figure 5. Eye Diagram Margin

Function of a practical speed limitation
The minimum bit time is an aggregate of a required minimum bit-valid timing window of a receiver and a minimum timing impact of a transmitter. The minimum bit time can be calculated as equation 6: T_min = F (slew rate, clock jitter, BER, skew) =R_samp+R_clkskew+R_pkgskew+R_chskew+T_rise + T_fall + T_chskew + T_pkgskew + T_pcbskew + T_totjitter

Because the R_clkjitter and T_clkjitter are not correlated jitter, the total clock jitter effect at an interface will be: T_totjitter = sqrt (T2_clkjitter + R2 _clkjitter)

Further, the maximum data speed is shown as equation 7: S_max =1/T_min.

Taking into account the impact of a transmitter and receiver clock jitter, channel skew and cross talk, the BER of an interface, power supply noise, device process, temperature, as well as EMI, then a practical data speed limitation can be derived from the minimum bit time and a specified eye diagram margin. Therefore, a practical data speed of a serial interface is a function of slew rate, clock jitter, interface BER, skew and eye diagram margin as illustrated as equation 8:

S = F (slew rate, clock jitter, BER, skew, E_margin) = 1/(T_min + T_margin )|A=A_margin

Single-channel A/D
The speed limitation is related to an interface BER, amplitude and timing margin. In the case of a single channel, there is no skew influence. The speed limitations are shown in Table 1. For example, a maximum data speed (S_max) can be by equation 7 as fast as 1.13GBPS with zero eye diagram margin, and BER=10^-7. But if taking into account a time margin 200ps and voltage margin 100mV threshold, a practical data speed limitation (S) can be degraded to around 840MBPS that is calculated with equation 8.

Table 1. Single-channel A/D serial interface speed limitation with BER and noise margin (A/D output current = 4.5mA, voltage margin/threshold 100mV, A/D output C=3pF, load C=8pF)

Multi-channel A/D
In the case of a multi-channel, the channel and package skew are an important contribution to the timing margin. The channel and package skew can be as long as 140ps in some cases. Although the maximum data speed limitation is 999MBPS, a practical speed can be degraded to around 603.9MBPS with voltage margin 100mV, timing margin 550ps and BER 10^-14.

A four-channel A/D example is shown in Table 2. For instance, the speed can be 664MBPS (55MSPS of 12 bit A/D) with voltage margin 100mV, timing margin 400ps and BER 10^-14.

The assumptions are R_samp=200ps, R_{clkjitter,p-p}=200ps, R_clkskew=25ps, P_pkgskew=22ps, T_skew=25ps, T_{clkjitter,rms}=25ps,T_pkgskew=30ps and T_pcb=20ps.

Table 2. Four-channel A/D serial interface speed limitation with BER and noise margin A/D output current = 4.5mA, voltage margin/threshold 100mV, A/D output C=3pF, load C=8pF)

An eight-channel A/D example is shown in Table 3. For instance, the speed can be 649.6MBPS (54.1MSPS of 12 bit A/D) with voltage margin 100mV, timing margin 400ps and BER 10^-14.

The assumptions are R_samp=200ps, R_{clkjitter,p-p}=200ps, R_clkskew 50ps, P_pkgskew=30ps, T_skew=25ps, T_{clkjitter,rms}=25ps,T_pkgskew=60ps and T_pcb=40ps.

Table 3. Eight-channel A/D serial interface speed limitation with BER and noise margin A/D output current = 4.5mA, voltage margin/threshold 100mV, A/D output C=3pF, load C=8pF)

Non-standard LVDS Interface
Increasing a data speed limitation means that the minimum bit time needs to be decreased. The minimum limits of clock jitter, channel-skew and parasitic capacitances have been determined by an available process and package. But the rise and fall time can be further reduced by increasing a slew rate. Increasing an output stage current of a transmitter will improve a slew rate, and eventually result in the increase of an interface data speed limitation. The standard LVDS has a specified maximum current of 4.54mA. The motivation of the following proposal is to increase transmitter current and to gain the maximum available data speed within an acceptable power dissipation and EMI range.

For example, Xilinx FPGA's LVDS input can accept a maximum 6mA current, if increasing the current of an A/D LVDS output stage from 4.5mA to 6mA, the transmission power is increased from 2mW to 3.6mW per channel, then the timing margin can be improved from 550ps to 650ps with the same speed 492MBPS (41MSPS of 12 bit A/D), a bigger transmitter clock jitter RMS value 50ps, and BER 10^-14.

If A/D designer can specify an input current of a receiver ASIC LVDS interface, then an A/D LVDS current may be further increased to 10mA from a standard LVDS. In that case slew rate will be almost doubled, and rise and fall time will be decreased by roughly two times. The minimum bit time will be decreased or timing margin will get bigger, and the maximum speed limitation will be increased significantly. The calculation results shown that a four-channel A/D with a non-standard 10mA LVDS can support a serial interface data rate 768MBPS (64MSPS of 12 bit A/D) with timing margin 400ps and BER 10^-14. In addition, an eight-channel A/D with a non-standard 10mA LVDS will provide a serial interface data rate 652.8MBPS (54.4MSPS of 12 bit A/D) with transmitter clock jitter RMS value 25ps, timing margin 400ps and BER 10^-14.

The drawback is that the non-standard 10mA LVDS maximum swing is +/-1V instead of +/-450mV and the transmitted maximum power consumption is 10mw per channel, but they may still be acceptable in some applications and they are much lower than a 3.3V CMOS output swing.

Multi Gigabit Interface

HyperTransport Interface
HyperTransport interface is a new high-speed, high-performance, chip-to-chip link for integrated circuits. It requires the implementation of physical layer, data link layer, transaction layer, session layer, and protocol layer functions.

Because a CRC is used in its data link layer, a receiver can detect some bit errors, therefore the tolerance of a BER will be larger, and the scaling factor for converting clock jitter RMS to peak-to-peak value will be smaller. On the other hand, the required eye diagram margin will be decreased. Thereby the fast data rate of 1.6Gbps per channel can be achieved with Hypertransport technology.

RocketIO Interface
RocketIO interface is based on MindSpeed's SkyRail technology and implemented in Xilinx FPGA. The RocketIO interface is designed to operate at any data rate in the range of 622Mbps to 3.125Gbps. It supports Fiber Channel, Gigabit Ethernet and Infiniband communications.

Except for all the basic functions of a physical layer and a data link layer has been implemented in the RocketIO interface, it also supports clock correction, channel bonding, 8B/10B code/decode, and embedded clock functions.

The differential output swing range of RocketIO interface is between 400mV and 800mV, and receiver impedance is programmable at 50 ohms or 75 ohms.

Evaluation criteria
An accurate BER test will require that a test system be designed for a transmitter to send pre-generated Pseudo Random Binary Sequence (PSBR) patterns, and a receiver to detect and check how many bit errors occur within a specified long-time period in order to achieve a statistical very low bit-error rate, such as 10^-14. The BER test can also verify long-time link stability. Normally, a transmitter repeatedly sends pre-created 1k to 20k PSBR patterns to a receiver.

Because of the number limitation of A/D registers, only a few BER test patterns can be built in the registers of an A/D for self-test, but the BER self-test with some repetitive patterns can still primarily verify LVDS interface performance and stability. A system level BER test can be implemented at a higher system level evaluation with a required PRBS patterns as long as 20k patterns.

For a characteristics test and evaluation purpose, an output clock jitter, channel-skew of an A/D LVDS serial interface need to be fully tested with a power supply noise tolerance. Recommended test condition is for a power supply ripple that varies in the range of 1mV and 50mV with a frequency from 20kHz to 2 MHz.

The minimum 50 dBc cross talk is recommended for all channel, and an impacted clock jitter caused by the cross talk needs to be evaluated. The SFDR, THD requirements for all the test equipment that includes test board, and FPGA deserializer used in this LVDS serial interface test system are recommended to be at least 95dBc.

Conclusion
This article has discussed some high-speed and high-density chip-to-chip connectivity issues in detail. It first defined a chip-to-chip inter-connection physical layer model, and secondly presented the calculation equations of a receiver and transmitter bit-valid timing window, as well as eye diagram margin. Thirdly, this paper elaborated the function of the maximum speed limitation as slew rate, clock jitter, required BER, skew, timing margin, and amplitude margin for single and multi-channel A/D cases. Fourthly, a non-standard 10mA LVDS proposal is recommended. Finally, HyperTrans port and RocketIO technology are illustrated for an ultra high-speed interface.

References
1. Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644-A-2001, Jan. 30, 2001
2. A. Boni, "LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-um CMOS" IEEE J. Solid-State Circuits Vol.36.pp.706-711, April 2001

About the author:
John Zhonghua Wu is a senior application engineer at Texas Instruments. He holds a Bachelor of Engineering degree in Electronic Engineering from University of Dalian, P.R. China and a Master of Science degree in Electronic Engineering from the Chinese Academy of Sciences. John can be reached at wu_john@ti.com.